1. Technical Field
The present invention relates generally to semiconductor device fabrication, and more particularly, to methods of forming of local and global wiring for semiconductor product.
2. Related Art
During semiconductor device fabrication many different circuits can be formed on a single semiconductor product, i.e., chip or wafer. Each circuit may have different requirements for back-end-of-line (BEOL) wiring, which includes wiring levels for scaling up wiring from lower levels. To illustrate one conventional process, reference is made to FIG. 1, which includes a table of steps for two circuits (or chips) A, B having different BEOL wiring requirements. Circuit A is designed to include six 1X ‘local wires’ (or ‘thinwires’) plus one 4X ‘global wire’ (or ‘fatwire’), and circuit B is designed to include two 1X local wires plus four 2X global wires and no 4X global wires. A ‘local wire’ is any wire that is substantially the same height and width as a first metal level wiring having a width X (hence, the 1X designation) and is sometimes referred to in the industry as a ‘thinwire’, and a “global wire” is any wire that is a multiple of the first metal level wiring greater than one, e.g., 2X, 4X, 8X, etc., and is sometimes referred to in the industry as a ‘fatwire’. Accordingly, the 2X global wires are nominally twice the height and width of local wires, 4X global wires are nominally four times the height and width of local wires, and so on.
As shown in FIG. 1, the conventional way to put the two circuits A, B on the same semiconductor product would be to process a total of eleven dual damascene copper (also aluminum or other metals) levels, requiring 11 metal depositions and 11 chemical mechanical polishing (CMP) steps. Essentially, one must process the six local wires required by circuit A, followed by the four 2X global wires required by circuit B, followed by the one 4X global wire required by circuit A. In addition, after the first two local wires are completed, circuit B would require that the circuitry somehow be “carried up” through the remaining four local wire levels required by circuit A to connect to the first 2X global wire. If no redesign is to be done, then the “carry-up” would probably be done through a series of special (vertical wiring level) reticles with vias and small metal islands (i.e., vertical wiring). Vertical wiring level reticles would also be needed for use on circuit A while the 2X levels for circuit B are being built, and for use on circuit B while the 4X level for circuit A is being built.
Based on the above description, building two circuits (or chips) on the same wafer with different BEOL wiring is fairly cumbersome and expensive due to the complex processing involved. Besides cost-inefficiency, the vertical wiring increases resistance and capacitance because of the liner required for all of the different wiring.
In view of the foregoing, there is a need in the art for methods of forming different BEOL wiring for different circuits (or chips) on the same wafer in a more cost-efficient and performance-enhancing manner.